Serial data input is enabled when the serial input enable terminal (IES*) of pin 9 is low, and serial data output is enabled when the serial output enable terminal (OES*) is low. Four data bits may be read into each FIFO buffer memory device 12-18 in a serial fashion on serial data input terminal (DS) of pin 7, and outputted in a serial fashion on the serial data output terminal (QS) of pin 22.
Data bits are entered into each of the FIFO buffer memory devices 12-18 on pins 18-21 in a parallel fashion when the parallel load (PL) terminal of pin 2 of each device is high, and may be outputted in a parallel fashion from pins 3, 4, 5 and 6 when the transfer out parallel (TOP) terminal of pin 13 is high. Each device 12, 14, 16 and 18 handles four data bits which may be entered or extracted asynchronously in serial or parallel fashion. The converter circuit includes four first-in, first-out (FIFO) buffer memory devices 12, 14, 16 and 18 which may be F9423 devices available from Fairchild.
2, form a schematic diagram of a serial-to-parallel and parallel-to-serial converter circuit of the present invention.
#Parallel to serial converter buffer code
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#Parallel to serial converter buffer pdf
Google Patents Serial-to-parallel and parallel-to-serial converterĭownload PDF Info Publication number US5134702A US5134702A US06/854,380 US85438086A US5134702A US 5134702 A US5134702 A US 5134702A US 85438086 A US85438086 A US 85438086A US 5134702 A US5134702 A US 5134702A Authority US United States Prior art keywords serial buffer memory fifo buffer data clocking Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US5134702A - Serial-to-parallel and parallel-to-serial converter US5134702A - Serial-to-parallel and parallel-to-serial converter
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